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1 of 26 december 20, 1999 ? 1999 integrated device technology, inc. *notice: the information in this document is subject to change without notice dsc 5607 advanced 64-bit microprocessors product family u high-performance 64-bit embedded microprocessor C 333mhz operating frequency C >440 dhrystone mips performance C 666mflops/s floating-point performance C up to 125 million multiply accumulate per second (mac/s) C mips-iv instruction set architecture (isa), with integer dsp and 3-operand integer multiply extensions C limited dual-issue microarchitecture u compatible with rc4640 and rc32364 dsp extensions C dsp extensions, for consumer applications C 2-cycle repeat rate, on atomic multiply-add C multiply-subtract (msub) support, for complex number processing C count-leading-zero/one support, for string searches and normalization u high-performance on-chip cache subsystem C 32kb, two-set associative instruction cache (i-cache) C 32kb, two-set associative data cache (d-cache) C write-through and write-back data cache operations C high-performance cache-ops, bandwidth management u i-cache and d-cache locking capability (per line), provides improved real-time support u joint tlb on-chip, for virtual-to-physical address mapping u big- or little-endian capability u rc5000 compatible memory management C on-chip 48-entry, 96-page tlb, for advanced operating system support C compatible with major operating systems: windows ? ce, vxworks, and others u bus compatible with idt 64-bit microprocessor families C pipeline runs at 2 to 8 times the bus frequency C bus speeds to 125mhz C 32-bit bus option, for lower cost systems C enhanced timing protocol for syncdram systems (compatible with idt79rc64474/475) u rc64574: C 32-bit sysad bus, for low-cost systems C pin compatible with rc4640 and rc64474 C 128-pin qfp package u rc64575: C 64-bit sysad bus interface C pin compatible with rc4650 and rc64475 C 208-pin qfp package u jtag boundary scan interface u 2.5v operation with 3.3v tolerant i/o

the idt logo is a registered trademark and rc32134, rc32364, rc64145, rc64474, rc64475, rc4650, rc4640, rc4600,rc4700 rc3081, r c3052, rc3051, rc3041, riscontroller, and riscore are trade- marks of integrated device technology, inc. 64-bit integer dsp accelerator execution unit 666 mfiops floating-point accelerator pll dual-issue instruction fetch unit primary cache controller rc5000 compatible system control coprocessor 48-entry 96-page tlb 32kb 2 set-associative instruction cache 32kb 2 set-associative data cache 64-bit/32-bit rc64474/475 compatible system interface clkin (lockable) (lockable) ieee 1284 rc64574 ? rc64575 ? preliminary information*
2 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice idts 79rc64574/575 processors serve a wide range of perfor- mance-critical embedded applications that include high-end internet- working systems, digital set-top boxes, web browsers, color printers, and graphics terminals. the rc64574/575 allow a socket compatible upgrade path for idts rc4640/50 and rc64474/475 processors. this unprecedented upgrad- ability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1 range of floating-point; and 4:1 range of dsp performance in a single socket. with special emphasis on system bandwidth, floating- point and dsp operations, the rc64574/575 have been optimized for high-perfor- mance applications through the integration of high-performance compu- tational units and a high-performance memory hierarchy. the result is a low-cost cpu that is capable of more than 400 dhrystone mips. through the rc64574/64575 processors idt offers: u high-performance upgrade paths to existing embedded customers in the internetworking, office automation and visualization markets. u significant floating-point performance improvements over currently available, moderately priced mips cpus. u performance improvements through the use of the mips-iv isa. u high-performance dsp acceleration 1. detailed system operation information is provided in the rc64574/rc64575 users manual.

the rc64574 and rc64575 are limited dual-issue super-scalar machines that use a traditional 5-stage integer pipeline, as shown in the pipeline diagram on page 3. for multi-issue operations, these devices recognize the following two general classes of instructions: u floating-point alu u all others such a broad separation of instruction classes insure that there are no data dependencies to restrict multi-issue performance. as they are brought on-chip, these instruction classes are pre-decoded by the rc64574/575, and the class information is then stored in the instruction cache. assuming there are no pending resource conflicts, the devices can issue one instruction per class per pipeline clock cycle. however, longer latency resourcesin either the floating-point alu (for example, division or square root instructions) or integer unit (such as multiply)can restrict the issue of instructions. note that these proces- sors do not perform out-of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. on dual-issue instruction pairs, there are no alignment restrictions, and the rc64574/575 fetch two instructions from the cache per cycle. thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, because the instruc- tion cache only performs aligned fetches.

cpu 64-bit riscore4000 w/ dsp extensions 64-bit riscore4000 64-bit riscore5000 w/ dsp extensions 64-bit riscore4000 w/ dsp extensions 64-bit riscore4000 64-bit riscore5000 w/ dsp extensions performance >350mips >330mips >440mips >350mips >330mips >440mips fpa 89 mflops, single preci- sion only 125 mflops, single and double precision 666 mflops, single and double precision 89 mflops, single preci- sion only 125 mflops, single and double precision 666 mflops, single and double precision caches 8kb/8kb, 2-way, lock- able by set 16kb/16kb, 2-way, lock- able by set 32kb/32kb, 2-way, lock- able by set 8kb/8kb, 2-way, lock- able by set 16kb/16kb, 2-way, lockable by set 32kb/32kb, 2-way, lockable by set external bus 32-bit 32-bit, superset pin compatible w/rc4640 32-bit, superset pin compatible w/rc4640, rc64474 32- or 64-bit 32-or 64-bit, superset pin compatible w/ rc4650 32-or 64-bit, superset pin compatible w/ rc4650, rc64475 voltage 3.3v 3.3v 2.5v 3.3v 3.3v 2.5v frequencies 100-267 mhz 180-250 mhz 200-333 mhz 100-267 mhz 180-250 mhz 250-333 mhz packages 128 pqfp 128 qfp 128 qfp 208 qfp 208 qfp 208 qfp mmu base-bounds 96 page tlb 96 page tlb base-bounds 96 page tlb 96 page tlb key features cache locking, on-chip mac, 32-bit external bus cache locking, jtag, syncdram mode, 32-bit external bus cache locking, jtag, syncdram mode, 32-bit external bus cache locking, on-chip mac, 32-bit & 64 bit bus option cache locking, jtag, syncdram mode, 32- 64- bit bus option cache locking, jtag, syncdram mode, 32- 64- bit bus option table 1 riscore4000/riscore5000 processor family
3 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice

the rc64574/575 implement a superset of the mips-iv 64-bit isa, including cp1 and cp1x functional units and their instruction set. both 32- and 64-bit data operations are performed by utilizing thirty-two general purpose 64-bit registers (gpr) that are used for integer opera- tions and address calculation. the complete on-chip floating-point co- processor (cp1)which includes a floating-point register file and execu- tion unitsforms a seamless interface, decoding and executing instructions in parallel with the integer unit. cp1s floating-point execution units support both single and double precision arithmeticas specified in the ieee standard 754 and are separated into a multiply unit and a combined add/convert/ divide/square root unit. overlap of multiplies and add/subtract is supported, and the multiplier is partially pipelined, allowing the initiation of a new multiply instruction every fourth pipeline cycle. the floating- point register file is made up of thirty-two 64-bit registers. the floating- point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every cycle. the system control coprocessor (cp0) registers are also incorpo- rated on-chip and provide the path through which the virtual memory systems page mapping is examined and changed, exceptions are handled, and any operating mode selections are controlled. a secure user processing environment is provided through the user, supervisor, and kernel operating modes of virtual addressing to system software. bits in a status register determine which of these modes is used. the integer instruction execution speed is tabulatedin number of pipeline clocksas follows: table 2 integer instruction execution speed to insure that the maximum frequency of operation is not limited by the speed of the multiplier unit, a fast multiply disable reset mode bit (see table 2) is featured. when this bit is asserted, each multiply opera- tion shown in table 1 has its latency and repeat rate increased by one cycle.

load 2 1 store 2 1 mult/multu 4 3 dmult/dmultu 6 5 div/divu 36 36 ddiv/ddivu 68 68 mad/madu 3 2 msub/msubu 4 3 other integer alu 1 1 branch 2 2 jump 2 2 load and branch latencies are minimized by the short pipeline of the rc64574/575, and the caches contain special logic that will allow any combination of loads and stores to execute in back-to-back cycles without requiring pipeline slips or stalls, assuming the operation does not miss in the cache.

! ! ! ! the rc64574/575 implement a full, single-cycle 64-bit arithmetic logic unit (alu), for integer alu functions other than multiply and divide. bypassing is used to support back-to-back alu operations at the full pipeline rate, without requiring stalls for data dependencies. to allow the longer latency operations to run in parallel with other operations, the integer multiply/divide unit of the rc64574/ 575 is separated from the primary alu. the pipeline stalls only if an attempt to access the hi or lo registers is made before an operation completes. the floating-point alu unit is responsible for all of the cp1/cp1x alu operationsother than div/sqrt operationsand is pipelined to allow a single-cycle repeat rate for single-precision operations. the floating-point div/sqrt unit is separated from the floating- point alu, to ensure that these longer latency operations do not prevent the issue of other floating-point operations. separate logical units are also provided on the rc64574/575 to implement load, store, and branch operations. intended to enhance the performance of dsp algorithms such as fast fused multiply-adds, multiply-subtracts and three operand multiply oper- ations , new instructions have been added over and above the mips-iv isa. " " " " # # # # the rc64575 supports a 64-bit system interface that is pin and bus compatible with the rc4650 and rc64475 system interface. the system interface consists of a 64-bit address/data bus with eight parity- check bits and a 9-bit command bus. during 64-bit operation, rc64575 system address/data (sysad) transfers are protected with an 8-bit parity check bus, sysadc. when initialized for 32-bit operation, the rc64575s sysad can be viewed as a 32-bit multiplexed bus that is protected by four parity-check bits. the rc64574 supports a 32-bit system interface that is pin and bus compatible with the rc4640 and rc64474. during 32-bit operation, sysad transfers are performed on a 32-bit multiplexed bus (sysad 31:0) that is protected by 4 parity check bits (sysadc 6:0). writes to external memorywhether they are cache miss write- backs, stores to uncached or write-through addressesuse the on-chip write buffer . the write buffer holds a maximum of four 64-bit addresses and 64-bit data pairs. the entire buffer is used for a data cache write- back and allows the processor to proceed in parallel with memory updates. included in the system interface are six handshake signals : rdrdy*, wrrdy*, extrqst*, release*, validout*, and validin*; six inter- rupt inputs, and a simple timing specification that is capable of trans-
4 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice ferring data between the processor and memory at a peak rate of 1000mb/sec. a boot-time selectable option to run the system interface as 32-bits wideusing basically the same protocols as the 64-bit systemis also supported. a boot-time mode control interface initializes fundamental processor modes and is a serial interface that operates at a very low frequency (sysclock divided by 256). this low-frequency operation allows the initialization information to be kept in a low-cost eprom; alternatively, the twenty-or-so bits could be generated by the system interface asic or a simple pal. the boot-time serial stream is shown in table 3.
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& 0 reserved must be set to 0. 1:4 transmit-data- pattern. bit 4 is msb 64-bit bus width: 0: dddd 1: ddxddx 2: ddxxddxx 3: dxdxdxdx 4: ddxxxddxxx 5: ddxxxxddxxxx 6: dxxdxxdxxdxx 7: ddxxxxxxddxxxxxx 8: dxxxdxxxdxxxdxxx 9-15: reserved. must not be selected. 32-bit bus width: 0: wwwwwwww 1: wwxwwxwwxwwx 2: wwxxwwxxwwxxwwxx 3: wxwxwxwxwxwxwxwx 4: wwxxxwwxxxwwxxxwwxxx 5: wwxxxxwwxxxxwwxxxxwwxxxx 6: wxxwxxwxxwxxwxxwxxwxxwxx 7: wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx 8: wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx 9-15: reserved. must not be selected. 5:7 pclock-to- sysclk-ratio. bit 7 is msb 0: 2 1: 3 2: 4 3: 5 4: 6 5: 7 6: 8 7: reserved 8 endianness 0: little endian 1: big endian 9:10 non-block write mode. bit 10 is msb 00: r4400 compatible 01: reserved 10: pipelined-write-mode 11: write-reissue-mode table 3 boot-time mode stream (page 1 of 2) the clocking interface allows the cpu to be easily mated with external reference clocks. the cpu input clock is the bus reference clock and can be between 33 and 125mhz. an on-chip phase-locked- loop (pll) generates the pipeline clock (pclock) through multiplication of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at system reset. this allows the pipeline clock to be implemented at a significantly higher frequency than the system interface clock. the rc64574/575 support both single data (one byte through full cpu bus width) and 8-word block transfers on the sysad bus. the rc64574/575 implement additional write protocols that double the effective write bandwidth . the write re-issue has a repeat rate of 2 cycles per write. pipelined writes have the same 2-cycle per write repeat rate, but can issue an additional write after wrrdy* de- asserts. 11 timerinten timer interrupt settings: 0: enable timer interrupt on int(5) 1: disable timer interrupt on int(5) 12 system interface bus width. interface bus width control settings: 0: 64-bit system interface 1: 32-bit system interface 13:14 drv_out bit 14 is msb slew rate control of the output drivers: 10: 100% strength (fastest) 11: 83% strength 00: 67% strength 01: 50% strength (slowest) 15:17 write address to write data delay. from 0 to 7 sysclk cycles: 0: ad... 1: axd... 2: axxd... 3: axxxd... 4: axxxxd... 5: axxxxxd... 6: axxxxxxd... 7: axxxxxxxd... 18 reserved user must select 0 19 extend multiplication repeat rate. initial setting of the fast multiply bit. 0: enable fast multiply 1: do not enable fast multiply note: for pipeline speeds >250mhz, this bit must be set to 1. 20:24 reserved user must select 0 25:26 system configuration identifier. software visible in processorconfig[21:20] 0: config[21:20] = mode bit [25:26] must be set to 0. 27:256 reserved user must select 0
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& table 3 boot-time mode stream (page 2 of 2)
5 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice choosing a 32- or 64-bit wide system interface dictates whether a cache line block transaction requires 4 double word data cycles or 8 single word cycles as well as whether a single data transferlarger than 4 bytesmust be divided into two smaller transfers. as shown in table 3, the bus delay can be defined as 0 to 7 sysclock cycles and is activated and controlled through mode bit (17:15) settings selected during the reset initialization sequence. the 000 setting provides the same write operations timing protocol as the rc4640, rc4650, and rc5000 processors. to facilitate discrete interface to syncdram , the rc64574/575 bus interface is enhanced during write cycles with a programmable delay that is inserted between the write address and the write data (for both block and non-block writes). board-level testing during run-time mode is facilitated through the full jtag boundary scan facility. five pinstdi, tdo, tms, tck, trst*have been incorporated to support the standard jtag inter- face. the rc64574/575 devices offer a direct migration path for designs that are based on idts rc4640/rc4650 and rc64474/rc64475 processors 2 , through full pin and socket compatibility. full 64-bit-family software and bus protocol compatibility ensures the rc64574/575 processors access to an existing market and development infrastruc- ture, allowing quicker time to market.

$ $ $ $

an array of hardware and software tools is available to assist system designers in the rapid development of rc64574/575 based systems. this accessibility allows a wide variety of customers to take full advan- tage of the devices high-performance features while addressing todays aggressive time-to-market demands.

" " " " to keep the high-performance pipeline of the rc64574/575 full and operating efficiently, on-chip instruction and data caches have been incorporated. each cache has its own data path and can be accessed in the same single pipeline clock cycle. the 32kb two-way set associative instruction cache is virtually indexed, physically tagged, and word parity protected. because this cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing both operations to occur simultaneously. the instruction cache provides a peak instruction bandwidth of 2667mb/sec at 333mhz. the 32kb two-way set associative data cache is byte parity protected and has a fixed 32-byte (eight words) line size. its tag is protected with a single parity bit. to allow simultaneous address transla- tion and data cache access, the d-cache is virtually indexed and physi- cally tagged. the data cache can provide 8 bytes each clock cycle, for a peak bandwidth of 2667mb/s. 2. to ensure socket compatibility, refer to table 8 and table 9. to lock critical sections of code and/or data into the caches for quick access, a per line cache locking feature has been implemented. once enabled, a cache is said to be locked when a particular piece of code or data is loaded into the cache and that cache location will not be selected later for refill by other data.

executing the wait instruction enables the processor to enter standby mode. the internal clocks will shut down, thus freezing the pipeline. the pll, internal timer, and some of the input pins (int[5:0]*, nmi*, extreq*, reset*, and coldreset*) will continue to run. once in standby mode, any interrupt, including the internally generated timer interrupt, will cause the cpu to exit standby mode. $ $ $ $

the rc64574 is packaged in a 128-pin qfp footprint package and uses a 32-bit external bus, offering the ideal combination of 64-bit processing power and 32-bit low-cost memory systems. the rc64575 is packaged in a 208-pin qfp footprint package and uses the full 64-bit external bus. the rc64575 is ideal for applications requiring 64-bit performance and 64-bit external bandwidth. both devices are guaranteed in a case temperature range of 0 to +85 c, for commercial temperature devices. package type, speed (power) of the device, and air flow conditions affect the equivalent ambient temperature conditions that will meet these specifications. using the thermal resistance from case to ambient ( ? ca ) of the given package, the equivalent allowable ambient temperature, t a , can be calculated. the following equation relates ambient and case temper- atures: t a = t c - p * ? ca where p is the maximum power consumption at hot temperature, calculated by using the maximum i cc specification for the device. typical values for ? ca at various air flow are shown in table 4. note that the rc64574/575 processor implements advanced power manage- ment, which substantially reduces the typical power dissipation of the device. % % % %

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" " " " july 22, 1999, rev. 1.0: original data sheet. september 9, 1999, rev. 1.1 : made several changes in jtag inter- face section of table 5. added information on pin 63 in table 5. ? ? ? ? ' '() *(+,- . / 128 qfp 16 10 9765 208 qfp 20 13 10 9 8 7 table 4 thermal resistance ( ? ? ? ? ca) at various airflows
6 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice october 14, 1999, rev. 1.2 : revised data in the power consump- tion tables for rc64574 and rc64575. november 16, 1999, rev. 1.3 : added power curve graphs, revised data in system interface parameters table, added system clock jitter row to clock parameter table. december 20, 1999, rev. 1.4 : table 7 rc64574 128-pin package on page 12, changed pin #75 function from vcc to n.c.
7 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice

$ $ $ $' ' ' ' the following is a list of system interface pins available on the rc64574/575. pin names ending with an asterisk (*) are active when low. 0 ,
1
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system interface extrqst* i external request an external agent asserts extrqst* to request use of the system interface. the processor grants the request by asserting release*. release* o release interface in response to the assertion of extrqst* or a cpu read request, the processor asserts release* and signals to the requesting device that the system interface is available. rdrdy* i read ready the external agent asserts rdrdy* to indicate that it can accept a processor read request. wrrdy* i write ready an external agent asserts wrrdy* when it can now accept a processor write request. validin* i valid input signals that an external agent is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. validout* o valid output signals that the processor is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. sysad(63:0) i/o system address/data bus a 64-bit address and data bus for communication between the processor and an external agent. in 64 bit interface mode, during address phases only, sysad(35:0) contains invalid address information. the remain- ing sysad(63:36) pins are not used. the whole 64-bit sysad(63:0) may be used during the data transfer phase. for all double-word accesses (read or write), the low-order 3 bits (sysad[2:0]) will always be output as zero during the address phase. in 32-bit interface mode and in the rc64574, sysad(63:32) is not used, regardless of endianness. a 32-bit address and data communication between processor and external agent is performed via sysad(31:0). sysadc(7:0) i/o system address/data check bus an 8-bit bus containing parity check bits for the sysad bus during data bus cycles. in 32-bit mode and in the rc64574, sysadc(7:4) is not used. the sysadc(3:0) contains check bits for sysad(31:0). syscmd(8:0) i/o system command/data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmdp i/o system command parity a single, even-parity bit for the syscmd bus. this signal is always driven low. clock/control interface sysclock i systemclock the system clock input establishes the processor and bus operating frequency. it is multiplied internally by 2,3,4,5,6,7, or 8 to generate the pipeline clock (pclock). v cc pi quiet vcc for pll quiet v cc for the internal phase locked loop. v ss pi quiet v ss for pll quiet v ss for the internal phase locked loop. table 5 pin descriptions (page 1 of 2)
8 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice interrupt interface int*(5:0) i interrupt six general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register. nmi* i non-maskable interrupt non-maskable interrupt, ored with bit 6 of the interrupt register. initialization interface v cc o ki v cc is ok when asserted, this signal indicates to the processor that the power supply has been above the vcc minimum for more than 100 milliseconds and will remain stable. the assertion of v cco k initiates the initialization sequence. coldreset* i cold reset this signal must be asserted for a power on reset or a cold reset. coldreset must be de-asserted synchro- nously with sysclock. reset* i reset this signal must be asserted for any reset sequence. it can be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. reset must be de-asserted synchronously with sysclock. modeclock o boot-mode clock serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six. modein i boot-mode data in serial boot-mode data input. jtag interface tdi i jtag data in on the rising edge of tck, serial input data are shifted into either the instruction register or data register, depending on the tap controller state. an external pull-up resistor is required. tdo o jtag data out on the falling edge of tck, the tdo is serial data shifted out from either the instruction or data register. when no data is shifted out, the tdo is tri-stated (high impedance). tck i jtag clock input an input test clock used to shift into or out of the boundary-scan register cells. tck is independent of the sys- tem and processor clock with nominal 40-60% duty cycle. tms i jtag command select the logic signal received at the tms input is decoded by the tap controller to control test operation. tms is sampled on the rising edge of tck. an external pull-up resistor is required. trst* i jtag reset the trst* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the pro- cessor logic. during normal cpu operation, the jtag controller will be held in the reset mode, asserting this active low pin. when asserted low, this pin will also tristate the tdo pin. an external pull-down resistor is required. jtag32* i jtag 32-bit scan this pin is used to control length of the scan chain for sysad (32-bit or 64-bit) for the jtag mode. when set to vss, 32-bit bus mode is selected. in this mode, only sysad(31:0) are part of the scan chain. when set to vcc, 64-bit bus mode is selected. in this mode, sysad(63:0) are part of the scan chain. this pin has a built-in pull-down device to guarantee 32-bit scan, if it is left un connected. jr_v cc i jtag vcc this pin has an internal pull-down to continuously reset the jtag controller (if left unconnected) bypassing the trst* pin. when supplied with vcc, the trst* pin will be the primary control for the jtag reset. 0 ,
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table 5 pin descriptions (page 2 of 2)
9 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice (
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) ) ) ) % % % % *+, *+, *+, *+,- - - -+ + + +. . . .% % % % * * * *+ + + +,-, ,-, ,-, ,-, figure 1 illustrates the direction and functional groupings for the processor signals. figure 1 logic symbol for rc64574/rc64575 sysad(63:0) sysclock coldreset* reset* v cc p v ss p initialization interface interrupt system interface clock/control interface rc64574/ logic symbol 64 6 interface sysadc(7:0) 8 nmi * int*(5:0) jtag interface tdi tms trst* tdo handshake signals rc64575 tck rdrdy* wrrdy* extrqst* release* validin* validout* syscmd(8:0) syscmdp 9 vccok modeclock modein jtag32* jr_vcc
10 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice % % % % * * * *+ + + +,-, ,-, ,-, ,-, /0 /0 /0 /01 1 1 1 2 2 2 2

pin names followed by an asterisk (*) are active when low. for maximum flexibility and compatibility with future designs, n.c. pins should be left floating. 2 2 2 2 1 n.c. 53 jtag32* 105 n.c. 157 n.c. 2 n.c. 54 n.c. 106 n.c. 158 n.c. 3 n.c. 55 n.c. 107 n.c. 159 sysad59 4 n.c. 56 n.c. 108 n.c. 160 coldreset* 5 n.c. 57 syscmd2 109 n.c. 161 sysad28 6 n.c. 58 sysad36 110 n.c. 162 v cc 7 n.c. 59 sysad4 111 n.c. 163 v ss 8 n.c. 60 syscmd1 112 n.c. 164 sysad60 9n.c. 61v ss 113 n.c. 165 reset* 10 sysad11 62 v cc 114 sysad52 166 sysad29 11 v ss 63 sysad35 115 extrqst* 167 sysad61 12 v cc 64 sysad3 116 v cc 168 sysad30 13 syscmd8 65 syscmd0 117 v ss 169 v cc 14 sysad42 66 sysad34 118 sysad21 170 v ss 15 sysad10 67 v ss 119 sysad53 171 sysad62 16 syscmd7 68 v cc 120 rdrdy* 172 sysad31 17 v ss 69 sysad2 121 modein 173 sysad63 18 v cc 70 int5* 122 sysad22 174 v cc 19 sysad41 71 sysad33 123 sysad54 175 v ss 20 sysad9 72 sysad1 124 v cc 176 v cc ok 21 syscmd6 73 v ss 125 v ss 177 sysadc3 22 sysad40 74 v cc 126 release* 178 sysadc7 23 v ss 75 int4* 127 sysad23 179 n.c. 24 v cc 76 sysad32 128 sysad55 180 tdi 25 sysad8 77 sysad0 129 nmi* 181 trst* 26 syscmd5 78 int3* 130 v cc 182 tck 27 sysadc4 79 v ss 131 v ss 183 tms 28 sysadc0 80 v cc 132 sysadc2 184 tdo 29 v ss 81 int2* 133 sysadc6 185 v cc p 30 v cc 82 sysad16 134 sysad24 186 v ss p 31 syscmd4 83 sysad48 135 v cc 187 sysclock 32 sysad39 84 int1* 136 v ss 188 v cc 33 sysad7 85 v ss 137 sysad56 189 v ss table 6 rc64575 208-pin qfp package pin-out (page 1 of 2)
11 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice 34 syscmd3 86 v cc 138 sysad25 190 sysadc5 35 v ss 87 sysad17 139 sysad57 191 sysadc1 36 v cc 88 sysad49 140 v cc 192 v cc 37 sysad38 89 int0* 141 v ss 193 v ss 38 sysad6 90 sysad18 142 n.c 194 sysad47 39 modeclock 91 v ss 143 sysad26 195 sysad15 40 wrrdy* 92 v cc 144 sysad58 196 sysad46 41 sysad37 93 sysad50 145 n.c. 197 v cc 42 sysad5 94 validin* 146 v cc 198 v ss 43 v ss 95 sysad19 147 v ss 199 sysad14 44 v cc 96 sysad51 148 sysad27 200 sysad45 45 n.c. 97 v ss 149 n.c. 201 sysad13 46 n.c. 98 v cc 150 jr_ v cc 202 sysad44 47 n.c. 99 validout* 151 n.c. 203 v ss 48 n.c. 100 sysad20 152 n.c. 204 v cc 49 n.c. 101 n.c. 153 n.c. 205 sysad12 50 n.c. 102 n.c. 154 n.c. 206 syscmdp 51 n.c. 103 n.c. 155 n.c. 207 sysad43 52 n.c. 104 n.c. 156 n.c. 208 n.c. 2 2 2 2 table 6 rc64575 208-pin qfp package pin-out (page 2 of 2)
12 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice % % % % * * * *+ + + +,-+ ,-+ ,-+ ,-+ / / / /1 1 1 1

n.c. pins should be left floating for maximum flexibility as well as for compatibility with future designs. an asterisk (*) ide ntifies a pin that is active when low. 2 2 2 2 1 jtag32* 33 v cc 65 v cc 97 v cc 2 syscmd2 34 v ss 66 sysad28 98 v ss 3v cc 35 sysad13 67 coldreset* 99 sysad19 4v ss 36 sysad14 68 sysad27 100 validin* 5 sysad5 37 v ss 69 v ss 101 v cc 6wrrdy* 38v cc 70 v cc 102 v ss 7 modeclock 39 sysad15 71 jr_v cc 103 sysad18 8 sysad6 40 v ss 72 sysad26 104 int0* 9v cc 41 v cc 73 n.c. 105 sysad17 10 v ss 42 sysadc1 74 v ss 106 v cc 11 syscmd3 43 v ss 75 n.c. 107 v ss 12 sysad7 44 v cc 76 sysad25 108 int1* 13 syscmd4 45 sysclock 77 v ss 109 sysad16 14 v cc 46 v ss p78v cc 110 int2* 15 v ss 47 v cc p 79 sysad24 111 v cc 16 sysadc0 48 tdo 80 sysadc2 112 v ss 17 syscmd5 49 tms 81 v ss 113 int3* 18 sysad8 50 tck 82 v cc 114 sysad0 19 v cc 51 trst* 83 nmi* 115 int4* 20 v ss 52 tdi 84 sysad23 116 v cc 21 syscmd6 53 v ss 85 release* 117 v ss 22 sysad9 54 sysadc3 86 v ss 118 sysad1 23 v cc 55 v cc ok 87 v cc 119 int5* 24 v ss 56 v ss 88 sysad22 120 sysad2 25 syscmd7 57 vcc 89 modein 121 v cc 26 sysad10 58 sysad31 90 rdrdy* 122 v ss 27 syscmd8 59 v ss 91 sysad21 123 syscmd0 28 v cc 60 v cc 92 v ss 124 sysad3 29 v ss 61 sysad30 93 v cc 125 v cc 30 sysad11 62 sysad29 94 extrqst* 126 v ss 31 syscmdp 63 reset* 95 sysad20 127 syscmd1 32 sysad12 64 v ss 96 validout* 128 sysad4 table 7 rc64574 128-pin package
13 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice % % % % * * * *+ + + +,-+ ,-+ ,-+ ,-+

' ' ' ' " " " "

% % % % *++ *++ *++ *++- - - -+ + + + 3 3 3 3 % % % % +*+0 +*+0 +*+0 +*+0 the rc64574/575 is 100% pin compatible with the rc64474/475 with the supply voltage being the only difference. rc64474/475 requ ires a 3.3v supply, while rc64574/575 requires a 2.5v supply. to ensure socket compatibility between the rc64574/rc64474 and the rc4640 devices, several pin changes are required, as shown i n the tables below. note: the rc64574/575 are 2.5v parts and as such all vcc must be at the correct voltage for a given part. % % % % * * * *+ + + +,-, ,-, ,-, ,-,

' ' ' ' " " " "

% % % % *++ *++ *++ *++- - - -, , , , 3 3 3 3 % % % % +*,0 +*,0 +*,0 +*,0 + ,
"3 ,,
1 n.c jtag32* yes. pin has an internal pull-down, to enable 32-bit scan. can also be left a n.c. 48 v ss tdo yes. can be driven with v ss , if jtag is not needed. is tristated when trst* is low. 49 v ss tms yes. can be driven with v ss if jtag is not needed. 50 v ss tck yes. can be driven with v ss if jtag is not needed. 51 v ss trst* yes. can be driven with v ss if jtag is not needed. 52 v ss tdi yes. can be driven with v ss if jtag is not needed. 71 n.c. jr_v cc yes. can be left n.c. in rc64574, if jtag is not need. if jtag is needed, it must be driven to v cc . table 8 rc64574 socket compatibility to rc64474 and r4640 " " ,
"3 ,,
53 n.c. jtag32* no connect jtag32* yes in 32-bit, this pin can be left uncon- nected because of internal pull-down. in 64-bit, this assumes that jtag will not be used. if using jtag, this pin must be at v cc . 150 n.c. jr_v cc no connect jr_v cc ye s in rc64475, can be left a n.c, if jtag is not need. if jtag is needed, it must be driven to v cc . 180 n.c. tdi no connect tdo yes if jtag is not needed, can be left a n.c. 181 n.c. trst* no connect trst* yes if jtag is not needed, can be left a n.c. 182 n.c. tck no connect tck yes if jtag is not needed, can be left a n.c. 183 n.c. tms no connect tms yes if jtag is not needed, can be left a n.c. 184 n.c. tdo no connect tdio yes if jtag is not needed, can be left a n.c. table 9 rc64575 socket compatibility to rc64475 & rc4650
14 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice ' ' ' '

4 4 4 4 % % % % note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. % % % %

$ $ $ $ " " " " 5 5 5 5

6 6 6 6 commercial temperature rangerc64574/575 (v cc = 2.5v 5%; t case = 0 c to +85 c) , & ,,
*4"56- 7 v term terminal voltage with respect to gnd C0.5 1 to +4.0 1. v in minimum = C2.0v for pulse width less than 15ns. v in should not exceed vcc +0.5 volts. v t c operating temperature (case) 0 to +85 c t bias case temperature under bias C55 to +125 c t stg storage temperature C55 to +125 c i in dc input current 20 2 2. when v in < 0v or v in > v cc . ma i out dc output current 50 3 3. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. ma 8 %
1
,

80! + commercial 0 c to +85 c (case) 0v 2.5v5% ,

$9: + $9: + $9: 1. at pipeline speeds >250mhz, the fast multiply bit must be disabled. + $9: % $ $ $ $ $ $ $ $ v ol 0.1v 0.1v 0.1v 0.1v |iout|= 20ua v oh v cc - 0.1v v cc - 0.1v v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v 0.4v 0.4v |iout|= 4ma v oh 2.0v 2.0v 2.0v 2.0v v il C0.5v 0.2v cc C0.5v 0.2v cc C0.5v 0.2v cc C0.5v 0.2v cc v ih 0.7 v cc 3.3v 0.7 v cc 3.3v 0.7 v cc 3.3v 0.7 v cc 3.3v i in 10ua 10ua 10ua 10ua 0 vin vcc c in 10pf 10pf 10pf 10pf c io 10pf 10pf 10pf 10pf c clk 10pf 10pf 10pf 10pf i/o leak 20ua 20ua 20ua 20ua input/output leakage
15 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice note: the following table assumes 4:1 pipeline to bus ratio. the following power curves provide the power values for different bus frequencies. note that the above table is based on a 4:1 pipeline-to-bus clock ratio. the following graph shows the power curves that provid e the power consumption at various bus frequencies. ,

$9: $9: $9: $9: % 1 1. typical integer instruction mix and cache miss rates $ 1 $ 1 $ 1 $ i cc stand-by 60 ma 2 2. these are not tested. they are the results of engineering analysis and are provided for reference only 60 ma 2 100 ma 2 100 ma 2 c l = 0pf 3 3. guaranteed by design. 120 ma 2 120 ma 2 120 ma 2 120 ma 2 c l = 50pf active 500 ma 2 600 ma 2 550ma 2 700 ma 2 700 ma 2 800ma 2 750 ma 2 900ma 2 c l = 0pf no sysad activity 3 vcc = 2.63v 550ma 2 650 ma 2 650 ma 2 800 ma 2 800ma 2 1000ma 2 850ma 2 1100ma 2 c l = 50pf r4x00 compatible writes, t c = 25 o c vcc = 2.63v 680 ma 2 850 ma 4 4. these are the specifications idt tests to insure compliance. 800 ma 2 1000 ma 4 950ma 2 1200ma 2 1000ma 2 1300ma 2 c l = 50pf pipelined writes or write re-issue, t c = 25 o c 3 vcc = 2.63v
16 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice note: the following table is for 4:1 pipeline to bus clock ratio. the following power curves provide the power consumption for vario us bus frequencies. note that the above table is based on a 4:1 pipeline-to-bus clock ratio. the following graph shows the power curves that provid e the power consumption at various bus frequencies. ,

$9: $9: $9: % 1 1. typical integer instruction mix and cache miss rates $ 1 $ 1 $ i cc stand-by 60 ma 2 2. these are not tested. they are the results of engineering analysis and are provided for reference only. 60 ma 2 100 ma 2 c l = 0pf 3 3. guaranteed by design. 120 m 2 a 120 ma 2 120 ma 2 c l = 50pf active, 64-bit bus option 4 4. in 32-bit bus option, use rc64574 power consumption values. 550 ma 2 700 ma 2 700 ma 2 800 ma 2 800 ma 2 1000 ma 2 c l = 0pf no sysad activity 3 vcc = 2.63v 800 ma 2 1000 ma 2 850 ma 2 1100 ma 2 900ma 2 1200ma 2 c l = 50pf r4x00 compatible writes, t c = 25 o c vcc = 2.63v 850 ma 2 1200 ma 5 5. these are the specifications idt tests to insure compliance. 950 ma 2 1300 ma 5 1200 ma 2 1500 ma 2 c l = 50pf pipelined writes or write re-issue, t c = 25 o c 3 vcc = 2.63v
17 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice $ $ $ $ ) ) ) )% % % % *+, *+, *+, *+,- - - -+ + + +. . . .% % % % * * * *+ + + +,-, ,-, ,-, ,-, figure 2 system clocks data setup, output, and hold timing figure 3 standard jtag timing cycle 1 2 3 4 sysclock t sysclk t sysclklow t sysclkp sysad,syscmd driven d d d t do sysad,syscmd received d d d d t ds t dh t doh sysadc control signal cpu driven validout* release * t do control signal cpu received rdrdy* wrrdy* extrqst* validin* t ds t dh nmi* int*(5:0) t doh sysadc t dz * = active low signal tdi/ tms tdo tdo tdo trst* tck t3 t1 t2 t ds t dh t do t4 t tck notes to diagram: t1 = t tcklow t2 = t tckhigh t4 = t rst (reset pulse width) t3 = t tckfall > = 25 ns t5 t5 = t tckrise
18 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice " " " " # # # #

# # # # ! ! ! ! " " " " # # # # $ $ $ $ figure 4 mode configuration interface reset sequence ,

, 1
% $9: + $9: + $9: + $9: 7 $ $ $ $ $ $ $ $ data output t do = max mode 14..13 = 10 (fastest) 5 4.3 4.3 4.3 ns mode 14..13 = 01 (slowest) 8 7 7 7 ns data output hold t doh 1 1. 50 pf loading on external output signals mode 14..13 = 10 (fastest) 1.0 1.0 1.0 1.0 ns data input t ds t rise = 3ns t fall = 3ns 222 2ns t dh 1.0 1.0 1.0 1.0 ns ,

, 1
% $9: + $9: + $9: + $9: % $ $ $ $ $ $ $ $ mode data setup t ds 4 4 4 4 sysclock cycle mode data hold t dh 0 0 0 0 sysclock cycle vcc coldreset* modebit[9:0] reset* >= 100 ms sysclock >= 10 ms >= 64 sysclk cycles
19 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice 6 6 6 6 (v cc = 2.5v 5%; t case = 0 c to +85 c)

% % % % & & & & " ' "' "' "'

,

, 1
% $9: + $9: + $9: + $9: 7 $ $ $ $ $ $ $ $ pipeline clock frequency pclk 100 200 100 250 100 300 100 333 mhz system clock high t schigh transition 3ns3333ns system clock low t sclow transition 3ns3333ns system clock frequency 33 100 33 125 33 125 33 125 mhz system clock period t scp 10308 308 308 30ns system clock jitter t jitter system clock rise time t scrise 2222ns system clock fall time t scfall 2222ns modeclock period t modeckp 256 t scp 256 t scp 256 t scp 256 t scp ns jtag clock input period t tck 100 100 100 100 ns jtag clock high t tckhigh 40 40 40 40 ns jtag clock low t tcklow 40 40 40 40 ns jtag clock rise time t tckrise 5555ns jtag clock fall time t tckfall 5555ns ,

, 1
% $9: $9: $9: $9: 7 $ $ $ $ $ $ $ $ load derate c ld 2 2 2 2 ns/25pf
20 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice ( ( ( ( & & & & " " " " # # # # ) ) ) ) * * * * # # # # & % all signals 50 pf C + to device under test c ld C4ma +4ma v ref +1.5v
21 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice % % % % * * * *+ + + +,-, ,-, ,-, ,-, /0 /0 /0 /01 1 1 1 the rc64575 is available in a 208-pin qfp package.
22 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice + + + + , , , ,- - - - # # # # ' ' ' ' # # # # . . . . # # # # + + + +/ / / /
23 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice % % % % * * * *+ + + +,-+ ,-+ ,-+ ,-+ / / / /1 1 1 1 7 7 7 7

# # # # 8 8 8 89 9 9 9 the rc64574 is available in a 128-pin qfp package.
24 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice 0 0 0 0+ + + +, , , ,- - - - # # # # ' ' ' ' # # # # . . . . # # # # + + + + 1 1 1 1/ / / /
25 of 26 december 20, 1999 rc64574? rc64575? *notice: the information in this document is subject to change without notice 0 0 0 0+ + + +, , , ,- - - - # # # # ' ' ' ' # # # # . . . . # # # # 1 1 1 1 1 1 1 1/ / / /
26 of 26 december 20, 1999 rc64574? rc64575? corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-5116 fax: 408-492-8674 www.idt.com for tech support: email: rischelp@idt.com phone: 408-492-8208 the idt logo is a registered trademark of integrated device technology, inc. *notice: the information in this document is subject to change without notice # # # #

2 2 2 2 " " " " idt79rc64t574 - 200, 250, 300, 333 dz 128-pin qfp package, commercial temperature idt79rc64t575 - 250, 300, 333 dp 208-pin qfp package, commercial temperature idt79rcxx yy xxxx 999 a a operating voltage device type speed package temp range/ process t 200 250 blank commercial temperature (0c to +85c case) 128-pin qfp 200 mhz pipeline clk 250 mhz pipeline clk 2.5v +/-5% embedded processor product type 79rc64 64-bit embedded microprocessor 208-pin qfp dp 300 300 mhz pipeline clk dz 574 333 mhz pipeline clk 333 575

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